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| HM514105D Series 4194304-word x 1-bit Dynamic RAM ADE-203-690(Z) Preliminary Rev. 0.0 Dec. 10, 1996 Description The Hitachi HM514105D is a CMOS dynamic RAM organized 4,194,304 word x 1-bit. HM514105D has realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM514105D offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input permits the HM514105D to be packaged in standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin plastic TSOP II. Features * * * * Single 5 V (10%) High speed Access time: 60 ns/70 ns (max) Low power dissipation Active mode: 715 mW/660 mW (max) Standby mode: 11 mW (max) EDO page mode capability 1024 refresh cycles : 16 ms 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Test function * * * * Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HM514105D Series Ordering Information Type No. HM514105DS-6 HM514105DS-7 HM514105DTT-6 HM514105DTT-7 Access time 60 ns 70 ns 60 ns 70 ns Package 300-mil 26-pin plastic SOJ (CP-26/20D) 300-mil 26-pin plastic TSOP II (TTP-26/20D) 2 HM514105D Series Pin Arrangement HM514105DS Series HM514105DTT Series Din WE RAS NC A10 1 2 3 4 5 26 25 24 23 22 VSS Dout CAS NC A9 Din WE RAS NC A10 1 2 3 4 5 26 25 24 23 22 VSS Dout CAS NC A9 A0 A1 A2 A3 VCC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 A0 A1 A2 A3 VCC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 (Top view) (Top view) Pin Description Pin Name A0 to A10 Function Address input -- Row A0 to A10 Column A0 to A10 Refresh A0 to A9 A0 to A9 Din Dout RAS CAS WE VCC VSS NC Refresh address input Data input Data output Row address strobe Column address strobe Read/Write enable Power supply Ground No connection 3 4 Row Driver Row Driver Block Diagram RAS RAS Control Circuit 256 k Memory Array Mat I/O Bus & Column Decoder Row Driver Row Driver 256 k Memory Array Mat HM514105D Series I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat Row Driver Row Driver CAS CAS Control Circuit 256 k Memory Array Mat Row Address Buffer Row Driver I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat WE WE Control Circuit Row Decoder & Peripheral Circuit Address A0-A10 Row Driver Row Driver Row Driver Row Driver Row Driver Row Driver Row Driver Row Driver 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat Din 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat Column Address Buffer I/O Buffer I/O Bus & Column Decoder Dout 256 k Memory Array Mat HM514105D Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to V SS . VIH VIL Min 0 4.5 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.5 6.5 0.8 Unit V V V V 1 1 1 Note 5 HM514105D Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM514105D -6 Parameter Operating current* Standby current 1, 2 -7 Max 110 2 Min -- -- Max 100 2 Unit mA mA Test Conditions RAS, CAS cycling t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA Symbol I CC1 I CC2 Min -- -- -- 1 -- 1 mA RAS-only refresh current*2 I CC3 Standby current* 1 -- -- -- -- -10 -10 2.4 0 110 5 110 130 10 10 VCC 0.4 -- -- -- -- -10 -10 2.4 0 100 5 100 120 10 10 VCC 0.4 mA mA mA mA A A V V I CC5 I CC6 CAS-before-RAS refresh current 3 EDO page mode current*1, I CC4 Input leakage current Output leakage current Output high voltage Output low voltage I LI I LO VOH VOL Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Input capacitance (Address, Data-in) Input capacitance (Clocks) Output capacitance (Data-out) Symbol CI1 CI2 CO Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout. 6 HM514105D Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *13, *14 Test Conditions * * * * * Input rise and fall time : 2 ns Input level : V IL = 0 V, V IH = 3.0 V Input timing reference levels : 0.8 V, 2.4 V Output timing reference levels : 0.8 V, 2.0 V Output load: 1 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM514105D -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Symbol t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP tT t REF Min 104 40 60 10 0 10 0 10 20 15 15 48 10 2 -- Max -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- 50 16 -7 Min 124 50 70 13 0 10 0 13 20 15 18 58 10 2 -- Max -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- 50 16 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 19 8 9 Notes 7 HM514105D Series Read Cycle HM514105D -6 Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time Output buffer turn-off time Turn-off to RAS Turn-off to WE Output data hold time Output data hold time from RAS Read command hold time from RAS Read command hold time from CAS Read command hold time from column address Symbol t RAC t CAC t AA t RCS t RCH t RRH t RAL t CAL t OFF t OFR t WEZ t OH t OHR t RCHR t RCHC t RCHA Min -- -- -- 0 0 0 30 18 -- -- -- 5 5 60 15 30 Max 60 15 30 -- -- -- -- -- 15 15 15 -- -- -- -- -- -7 Min -- -- -- 0 0 0 35 23 -- -- -- 5 5 70 18 35 Max 70 18 35 -- -- -- -- -- 15 15 15 -- -- -- -- -- ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6, 17 6, 17 6 16 16 Notes 2, 3, 15 3, 4, 12, 15 3, 5, 12, 17 Write Cycle HM514105D -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns Notes 10 8 HM514105D Series Refresh Cycle HM514105D -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol t CSR t CHR t RPC t CPN Min 10 10 10 10 Max -- -- -- -- -7 Min 10 10 10 13 Max -- -- -- -- Unit ns ns ns ns Notes EDO Page Mode Cycle HM514105D -6 Parameter EDO page mode cycle time EDO page mode CAS precharge time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low Read command hold time from CAS precharge Symbol t HPC t CP t RASC t ACP t RHCP t DOH t RCHP Min 25 10 -- -- 35 3 35 Max -- -- -7 Min 30 13 Max -- -- Unit ns ns 11 3, 12, 15 Notes 18 100000 -- 35 -- -- -- -- 40 3 40 100000 ns 40 -- -- -- ns ns ns ns Test Mode Cycle HM514105D -6 Parameter Test mode WE setup time Test mode WE hold time Symbol t WS t WH Min 0 10 Max -- -- -7 Min 0 10 Max -- -- Unit ns ns Notes 9 HM514105D Series Notes: 1. AC measurements assume t T = 2 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. 11. t RASC defines RAS pulse width in EDO page mode cycles. 12. Access time is determined by the longest among t AA , t CAC and t ACP. 13. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 14. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits - - - RA10, CA10 and CA0. This test mode operation can be performed by WE-and-CASbefore-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is Dout and data input pin is Din. In order to end this test mode operation, perform a CAS-before-RAS refresh cycle or a RAS-only refresh cycle. 15. In a test mode read cycle, the value of tRAC , t AA , t CAC and t ACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 16. Either t RCH or tRRH must be satisfied 17. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and t OH, and between tOFF and t OFR . 18. t HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page mode read cycles. 19. t CSH (min) can be achieved when tRCD tCSH (min) - tCAS (min). 20. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout 10 HM514105D Series Timing Waveforms*20 Read Cycle t RC t RAS RAS tT t RCD t RSH t CAS t CSH t RP t CRP CAS t RAD t ASR t RAH t ASC t RAL t CAH Address Row Column t CAL t RCS t RCHR t RCHC t RCHA t OH t OHR t RCH t RRH t CAC t AA t OFR t OFF Dout t RAC t WEZ WE Dout 11 HM514105D Series Early Write Cycle t RC t RAS RAS tT t RCD t CSH CAS t RSH t CAS t CRP t RP t ASR t RAH tASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) 12 HM514105D Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC tCRP CAS t ASR t RAH Address Row Dout High-Z CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC CAS t CPN WE t WS t WH t CPN t CSR tT t CHR t RPC t CRP t RAS t RP Address t OFR t OFF Dout High-Z 13 HM514105D Series Hidden Refresh Cycle tRC t RAS (Read) t RC t RP t RAS (Refresh) t RC t RP t RAS (Refresh) tRP RAS tT t RSH t RCD CAS t ASC t ASR t RAD t RAH Address Row t RAL t CAH Column t RCH t RRH t OHR t CAC t AA t RAC Dout Dout t WEZ t OFF t OH t CAS t CHR t CRP t RCS WE 14 HM514105D Series EDO Page Mode Read Cycle (tHPC minimum cycle operation) t RASC t RHCP t RP RAS tT t CSH t RCD CAS t ASR t RAD t RAH Address Row tASC t CAL t CAH Column 1 t CAL t ASC t CAH Column 2 t ASC t CAL t RAL t CAH Column 3 t RCHA t RCS WE t WEZ t CAC t CAC t RAC t AA t AA t ACP t DOH Dout Dout 1 t CAC t AA t ACP t DOH Dout 2 t OFF Dout 3 t OFR t RCHP t RCHC t RRH t RCH t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP t OH t OHR 15 HM514105D Series EDO Page Mode Early Write Cycle (tHPC minimum cycle operation) t RASC t RP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column Column Column t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din Din Din Dout High-Z 16 HM514105D Series Test Mode Cycle *,** Reset Cycle Set Cycle** Test Mode Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din: H or L 17 HM514105D Series Test Mode Set Cycle WE-and-CAS-Before RAS-Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR tT t CHR t RPC t CRP t CPN t WS t WH WE Address t OFF t OFR Dout High-Z 18 S C , S R P C B @ t CPN CAS HM514105D Series Package Dimensions HM514105DS Series (CP-26/20D) Unit: mm 26 16.90 17.27 Max 22 18 14 7.62 0.13 1 3.50 0.26 5 0.74 1.30 Max 9 13 0.21 2.40 + 0.24 - 8.51 0.13 0.80 +0.25 -0.17 6.71 0.28 Hitachi Code JEDEC Code EIAJ Code Weight CP-26/20D MO-077-AA SC-633A 0.6 g 0.43 0.10 0.41 0.08 5.08 0.10 1.27 19 HM514105D Series HM514105DTT Series (TTP-26/20D) Unit: mm 17.14 17.54 Max 26 22 18 14 7.62 1 5 1.27 0.42 0.08 0.40 0.06 0.21 1.15 Max 0.17 0.05 0.125 0.04 0.13 0.05 1.20 Max 5.08 0.10 0 - 5 0.50 0.10 M 9 13 0.80 9.22 0.20 Hitachi Code JEDEC Code EIAJ Code Weight TTP-26/20D MO-132AA -- 0.32 g 20 HM514105D Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 21 HM514105D Series Revision Record Rev. 0.0 Date Dec. 10, 1996 Contents of Modification Initial issue Drawn by Approved by 22 |
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